Search/CVE-2025-54520
CVE

CVE-2025-54520

Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality.

CVSS v3.1
EPSS
0.20%
probability of exploitation in 30 days
CISA KEV
Not listed
no confirmed exploitation reported
News coverage
0
sources referencing this CVE
EPSS Trend
Aug 16, 2026Aug 26, 2026
0.01pp
0.18% → 0.20% over 2 tracked changes
Connections
1 relationships
Timeline
disclosure → media coverage
Sep 24, 2025
Disclosure — published as a CVE record. · last revised by NVD Apr 15, 2026